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compact +30 v / 15 v 256-position digital potentiometer data sheet ad5290 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005-2011 analog devices, inc. all rights reserved. features 256 position 10 k, 50 k, 100 k +20 v to +30 v single-supply operation 10 v to 15 v dual-supply operation 3-wire spi?-compatible serial interface low temperature coefficient 35 ppm/c typical thd 0.006% typical midscale preset compact msop-10 package automotive temperature range: ?40c to +125c i cmos? 1 process technology applications high voltage dac programmable power supply programmable gain and offset adjustment programmable filters and delays actuator control audio volume control mechanical potentiometer replacement functional block diagram v dd a w b v ss sdi clk cs sdo dgnd por 8 8 rs 8-bit latch 8-bit serial register q d ck ad5290 04716-001 figure 1. general description the ad5290 is one of the few high voltage, high performance, and compact digital potentiometers 2, 3 in the market at present. this device can be used as a programmable resistor or resistor divider. the ad5290 performs the same electronic adjustment function as mechanical potentiometers, variable resistors, and trimmers, with enhanced resolution, solid-state reliability, and superior temperature stability. with digital rather than manual control, the ad5290 provides layout flexibility and allows closed-loop dynamic controllability. the ad5290 is available in msop-10 package and has 10 k, 50 k, and 100 k options. all parts are guaranteed to operate over the ?40c to +125c extended automotive temperature range. 1 i cmos? process technology. for analog systems designers who need high performance ics at higher voltage levels, i cmos is a technology platform that enables the development of analog ics capable of 30 v and operating at 15 v supplies while allowing dramatic reductions in power consumpti on and package size, and increased ac and dc performance. 2 the terms digital potentiometer and rdac are used interchangeably. 3 the rdac segmentation is protected by u.s. patent number 5,495,245.
ad5290 data sheet rev. c | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 10 k ? version ................................ 3 electrical characteristics 50 k?, 100 k ? versions ............... 5 interface timing characteristics ................................................ 7 3- wire digital interface ................................................................... 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and descriptions ............................................ 10 typical performance characteristics ........................................... 11 theory of op eration ...................................................................... 15 programming the variable resistor ......................................... 15 programming the potentiometer divider ............................... 16 3- wire serial bus digital interface .......................................... 16 daisy chain operation .............................................................. 16 esd protection ........................................................................... 17 terminal voltage operating range ......................................... 17 power - up and power - down sequences .................................. 17 layout and p ower supply biasing ............................................ 17 applications ..................................................................................... 18 high voltage dac ...................................................................... 18 progr ammable power supply ................................................... 18 audio volume control .............................................................. 18 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 11 /11 rev. b to rev. c c hang e to figure 33 ....................................................................... 18 4/10 rev. a to rev. b changes to figure 29 ...................................................................... 16 updated outline dimensions ....................................................... 20 7/ 09 rev. 0 to rev. a changes to features section ............................................................ 1 chang es to ordering guide .......................................................... 20 12/05 revision 0: initial version
data sheet ad5290 rev. c | page 3 of 20 specifications electrical character istics 10 k ? version v dd /v ss = 15 v 10%, v a = v dd , v b = v ss or 0 v, ?40c < t a < +125c, unless otherwise noted. table 1. parameter sym bol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nl 2 r- dnl r wb , v a = nc ?1 0.3 +1 lsb resistor nonlinearity 2 r- inl r wb , v a = nc ?1.5 0.7 +1 .5 lsb nominal resistor tolerance ? r ab t a = +25c ? 30 +30 % resistance temperature coefficient 3 (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect 35 ppm/c wiper resistance r w 50 100 ? dc characteristics potentiometer divider mode integral nonlinearity 4 inl ?1 0.3 +1 lsb d ifferential nonlinearity 4 dnl ?1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = 0x80 5 p pm/c full - scale error v wfse code = 0xff ? 6 ? 4 0 lsb zero - scale error v wzse code = 0x00 0 +3 +5 lsb resistor terminals voltage range 5 v a, b, w v ss v dd v capacitance 6 a, b c a, b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf common - mode leakage i cm v a = v b = v w 1 na digital inputs and outputs input logic high ( cs , clk, sdi) v ih 2.4 v input logic low ( cs , clk, sdi) v il 0.8 v output logic high (sdo) v oh r pull - up = 2.2 k? to 5 v 4.9 v output logic low (sdo) v ol i ol = 1.6 ma 0.4 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies positive supply current i dd v ih = +5 v or v il = 0 v, v dd /v ss = 15 v 15 50 a negative supply current i ss v ih = +5 v or v il = 0 v, v dd /v ss = 15 v ? 0.01 ? 1 a power dissipation 7 p diss v ih = +5 v or v il = 0 v, v dd /v ss = 15 v 765 w power supply rejection ratio psrr v dd /v ss = 15 v 10% ?0.15 0.08 +0. 15 %/%
ad5290 data sheet rev. c | page 4 of 20 parameter sym bol conditions min typ 1 max unit dynamic characteristics 6 , 8 , 9 bandwidth ?3 db bw code = 0x80 470 khz total harmonic distortion th d w v a = 1 v rms, v b = 0 v, f = 1 khz 0.006 % v w settling time t s v a = 10 v, v b = 0 v, 1 lsb error band 4 s resistor noise voltage e n_wb r wb = 5 k?, f = 1 khz 9 nv/hz 1 typical represents average reading at +25 c, v dd = +15 v, and v ss = ? 15 v. 2 resistor position nonlinearity error r - inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from an ideal value measured between succes sive tap positions. parts are guaranteed monotonic. 3 all p arts have a 35 ppm/c temperature coefficient. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac . v a = v dd and v b = 0 v. dnl spec ification limits of 1 lsb maximum are g uaranteed m ono tonic operating conditions. 5 resistor terminal a, terminal b, and terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ) + abs (i ss v ss ). cmos logic - level inputs result in minimum power dissipation. 8 bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. the lowest r value results in the fastest settli ng time and highest bandwidth. the highest r value results in the minimum overall power consumption. 9 all dynamic characteristics use v dd = +15 v and v ss = ?15 v.
data sheet ad5290 rev. c | page 5 of 20 electrical character istics 50 k ?, 100 k ? versions v dd /v ss = 15 v 10%, v a = +v dd , v b = v ss or 0 v, ?40c < t a < +125c, u nless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nl 2 r- dnl r wb , v a = nc ?0.5 0. 1 +0.5 lsb resistor nonlinearity 2 r- inl r wb , v a = nc ?1 0.5 +1 lsb nominal resistor tolerance ?r ab t a = +25c ?30 +30 % resistance temperature coefficient 3 (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect 35 ppm/c wiper resista nce r w 5 0 1 00 ? dc characteristics potentiometer divider mode integral nonlinearity 4 inl ? 1 0.5 +1 lsb differential nonlinearity 4 dnl ?1 0.5 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 cod e = 0x80 5 ppm/c full - scale error v wfse code = 0xff ?2.5 ?1.6 0 lsb zero - scale error v wzse code = 0x00 0 +0.6 +1 .5 lsb resistor terminals voltage range 5 v a, b, w v ss v dd v capacitance 6 a, b c a, b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf common - mode leakage i cm v a = v b = v w 1 na digital inputs and outputs input logic high ( cs , clk, sdi) v ih 2.4 v input logic low ( cs , clk, sdi) v il 0.8 v output logic high (sdo) v oh r pull - up = 2.2 k? to 5 v 4.9 v output logic low (sdo) v ol i ol = 1.6 ma 0.4 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies positive supply current i dd v ih = +5 v or v il = 0 v, v dd /v ss = 15 v 15 50 a negative supply current i ss v ih = +5 v or v il = 0 v, v dd /v ss = 15 v ?0.01 ?1 a power dissipation 7 p diss v ih = +5 v or v il = 0 v, v dd /v ss = 15 v 765 w power supply rejection ratio psrr v dd /v ss = 15 v 10% ?0.05 0. 01 +0. 05 %/%
ad5290 data sheet rev. c | page 6 of 20 parameter symbol conditions min typ 1 max unit dynamic characteristics 6 , 8 , 9 bandwidth ?3 db bw r ab = 50 k?, code = 0x80 90 khz r ab = 100 k?, code = 0x80 50 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.002 % v w settling time t s v a = 10 v, v b = 0 v, 1 lsb error band 4 s resistor noise voltage e n_wb r wb = 25 k?, f = 1 khz 20 nv hz 1 typical represent s average reading at +25c, vdd = +15 v, and vss = ?15 v. 2 resistor position nonlinearity error r - inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r -d nl measures the relative step change from an ideal value measured between successive tap positions. parts are guaranteed mono tonic. 3 all parts have a 35 ppm/c temperature coefficient. 4 inl and dnl are measured at vw with the rdac configured as a potentiometer divider similar to a voltage output dac . va = vdd and vb = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminal a, terminal b, and terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ) + abs (i ss v ss ). cmos logic level inputs result in minimum power dissipation. 8 bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. the lowest r value results in the fastest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 9 all dynamic characteristics use vdd = +15 v and vss = ?15 v.
data sheet ad5290 rev. c | page 7 of 20 interface timing characteristics table 3. p arameter 1 , 2 symbol conditions min typ max unit clock frequency f clk 4 mhz input clock pulse width t ch , t cl clock level high or low 120 ns data setup time t ds 30 ns data hold time t dh 20 ns clk to sdo propagation delay 3 t pd r pull - up = 2.2 k?, c l < 20 pf 10 100 ns cs setup time t css 120 ns cs high pulse width t csw 150 ns clk fall to cs fall hold time t csh0 10 ns clk rise to cs ris e hold time t csh 120 ns cs rise to clock rise setup t cs1 120 ns 1 see figure 3 for the location of the measured values. all input control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. switching characte ristics are measured using v dd = +15 v and v ss = ?15 v. 2 guaranteed by design and not subject to production test. 3 propagation delay depends on the value of v dd , r pull -up , and c l .
ad5290 data sheet rev. c | page 8 of 20 3- wire digital interfa ce data is loaded msb first. table 4. ad5290 serial data - word for mat b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb 2 7 2 0 d7 d6 d5 d4 d3 d2 d1 d0 1 sdi 0 1 clk 0 1 cs 0 1 v out 0 04716-002 rdac register load figure 2 . ad5290 3- wire digital interface timing diagram (v a = v dd , v b = 0 v, v w = v out ) 1 lsb error band 1 lsb t s t csw t csh t cl v dd v out 0v cs 0 1 t csh0 t css t ch 0 1 1 0 0 1 sdi (data in) sdo (data out) clk d x d x t ds t dh d' x d' x t pd_max t cs1 04716-003 figure 3 . detail timing diagram
data sheet ad5290 rev. c | page 9 of 20 absolute maximum rat ings t a = +25 c, unless otherwise noted. table 5. parameter rating v dd to gnd ? 0.3 v, +35 v v ss to gnd +0.3 v, ?16.5 v v dd to v ss ? 0.3 v, +35 v v a , v b , v w to gnd v ss , v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 6 k? , a open, 5 ma v dd /v ss = 30 v/0 v) 1 i wa continuous (r wa 6 k? , b open, 5 ma v dd /v ss = 30 v/0 v) 1 digital input and output voltag es to gnd 0 v, +7 v operating temperature range ? 40c to +125c maximum junction temperature (t jmax ) 2 +150c storage temperature ? 65c to +150c lead temperature (soldering, 10 sec to 30 sec) 245c thermal resistance 2 ja : msop -10 230c/w 1 the maximum terminal current is bound by the maximum current handling of t he switches, maximum power dissipation of the package, and the maximum applied voltage across any two of the following at a given resistance: a terminal, b terminal, and w terminal. 2 package power dissipation = (t jmax C t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera tional section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5290 data sheet rev. c | page 10 of 20 pin configuration and descriptions 04716-004 a 1 b 2 v ss 3 gnd 4 cs 5 w 10 v dd 9 sdo 8 sdi 7 clk 6 ad5290 top view (not to scale) figure 4 . ad5290 pin configuration table 6. ad5290 pin function descriptions pin no. mnemonic description 1 a a terminal. v ss v a v dd . 2 b b terminal. v ss v b v dd . 3 v ss negative supply. connect to 0 v for single - supply applications. 4 gnd digital ground. 5 cs chip select input ; a ctive l ow. when cs returns high, data is loade d into the wiper register. 6 clk serial clock input. positive edge triggered. 7 sdi serial data input pin. shifts in one bit at a time on positive clock clk edges. msb loaded first. 8 sdo serial data output pin. internal n - ch fet with open - drain output that requires external pull - up resistor. it shifts out the previous eight sdi bits that allow daisy - chain operation of multiple packages. 9 v dd positive power supply. 10 w w terminal. v ss v w v dd .
data sheet ad5290 rev. c | page 11 of 20 typical performance characteristics 1.0 ?1.0 0 04716-029 code (decimal) rheostat mode inl (lsb) 256 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ? 0.6 ?0.8 32 64 96 128 160 192 224 v dd = 16.5v ?40c +25c +125c figure 5 . resistance step position nonlinearity error vs. code 1.0 ?1.0 0 04716-030 code (decimal) rheostat mode dnl (lsb) 256 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ? 0.6 ?0.8 32 64 96 128 160 192 224 v dd = 16.5v ?40c +25c +125c figure 6 . resistance step change differential nonlinearity error vs. code 1.0 ?1.0 0 04716-031 code (decimal) potentiometer mode inl (lsb) 256 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 32 64 96 128 160 192 224 v dd = 16.5v ?40c +25c +125c figur e 7 . potentiometer divider nonlinearity error vs. code 1.0 ?1.0 0 04716-032 code (decimal) potentiometer mode dnl (lsb) 256 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ? 0.6 ?0.8 32 64 96 128 160 192 224 v dd = 16.5v ?40c +25c +125c figure 8 . potentiometer divider differential nonlinearity error vs. code 20 ?4 ?40 04716-005 temperature (c) supply current (a) 16 12 8 4 0 ?20 0 20 40 60 80 100 120 i dd @ v dd /v ss = 30v/0v i dd @ v dd /v ss = 15v i ss @ v dd /v ss = 30v/0v i ss @ v dd /v ss = 15v figure 9 . supply current i dd vs. temperature ?40 04716-007 total resistance, r ab (k?) ?20 0 20 40 60 80 100 120 120 100 80 60 40 20 0 temperature (c) 10k? 50k? 100k? v dd /v ss = 15v figure 10 . total resistance vs. temperature
ad5290 data sheet rev. c | page 12 of 20 100 ?100 0 04716-033 code (decimal) rheostat mode tempco (ppm/ c) 256 80 60 40 20 0 ? 20 ?40 ?60 ?80 32 64 96 128 160 192 224 10k 50k 100k figure 11 . ( r wb /r wb )/ t rheostat mode tempco 100 ?100 0 04716-034 code (decimal) potentiometer mode tempco (ppm/ c) 256 80 60 40 20 0 ? 20 ?40 ?60 ?80 32 64 96 128 160 192 224 10k 50k 100k figure 12 . ( v wb /v wb )/ t potentiometer mode tempco 0 ?60 1k 04716-022 (hz) (db) 1m 10k 100k ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 13 . 10 k? gain vs. frequency vs. code 0 ?60 1k 04716-023 (hz) (db) 1m 10k 100k ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 14 . 50 k? gain vs. frequency vs. code 0 ?60 1k 04716-024 (hz) (db) 1m 10k 100k ?6 ?12 ?18 ? 24 ?30 ?36 ?42 ?48 ?54 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 15 . 100 k? gain vs. frequency vs. code 04716-035 figure 16 . midscale transition glitch
data sheet ad5290 rev. c | page 13 of 20 ?60 0 100 04716-036 frequency (hz) power supply rejection ratio (db) 1m 1k 10k 100k ?40 ?20 code = 80 h , v dd /v ss = 15v, v a /v b = 10v ?psrr @ v dd /v ss = 15v dc 10% p-p ac +psrr @ v dd /v ss = 15v dc 10% p-p ac figure 17 . power supply rejection vs. frequency 1 0.0001 10 04716-009 frequency (hz) thd + n (%) 100k 100 1k 10k 0.001 0.01 10k? 50k? 100k ? v dd /v ss = 15v code = midscale v in = 1v rms figure 18 . total harmonic distortion plus noise vs. frequency 1 0.001 0.001 04716-010 amplitude (v) thd + n (%) 10 0.01 0.1 1 0.01 0.1 v dd /v ss = 15v code = midscale f in = 1khz 10k? 50k? 100k ? figure 19 . total harmonic distortion plus noise vs . amplitude 6 0 0 04716-027 code (decimal) theoretical i wb_max (ma) 256 5 4 3 2 1 64 128 192 v dd /v ss = 30v/0v v a = v dd v b = 0v r ab = 10k? r ab = 50k? r ab = 100k? figure 20 . theoretical maximum current vs. code 140 0 10k 04716-037 frequency (hz) supply current i dd (a) 10m 100k 1m 120 100 80 60 40 20 v dd = +15v v ss = ?15v v dig = +5v code = ff code = aa figure 21 . supply current i dd vs. frequency 10 0 10k 04716-038 frequency (hz) supply current i ss (na) 10m 100k 1m v dd = +15v v ss = ?15v v dig = +5v code = ff code = aa 8 6 4 2 figure 22 . supply current i ss vs. frequency
ad5290 data sheet rev. c | page 14 of 20 1000 10 0 04716-039 digital input voltage v ih (v) supply current i dd (a) 5 100 1 2 3 4 v dd /v ss = 16.5v figure 23 . supply current vs. digital input voltage 04716-040 figure 24 . digital feedthrou gh 04716-041 figure 25 . large signal settling time, code = 0x00 to 0xff
data sheet ad5290 rev. c | page 15 of 20 theory of operation programming the vari able resistor rheostat operation the part operates in the rheostat mode when only two termi - nals are used as a variabl e resistor. the unused terminal can be floating or tied to the w terminal as shown in figure 26 . a w b a w b a w b 04716-011 figure 26 . rheostat mode configuration the nomi nal resistance between terminal a and terminal b, r ab , is available in 10 k?, 50 k?, and 100 k? with 30% toler - ance and has 256 tap points accessed by the wiper terminal. the 8- bit data in the rdac latch is decoded to select one of the 256 possible settings. figure 27 shows a si mplified rdac structure. 4r s 4r s 4r s 2r s 2r s r s r w r w w r s 2r s 2r s 4r s 4r s a r w b 8-bit address decoder 04716-012 figure 27 . ad5290 simplified rdac circuit. (r s = s tep resistor , r w = w iper r esistor ) in order to achieve optimum cost performance, analog devices has patente d the rdac segmentation architecture for all the digital potentiometers . in particular, the ad5290 employ s a 3- stage segmentation approach as shown in figure 27. as a result, t he g eneral equation determining the digitally programmed output resistance between the w terminal and b terminal is w ab wb rr d dr += 3 256 )( (1) where: d is the decimal equivalent of the binary code loaded in the 8-b it rdac register from 0 to 255. r ab is the en d- to - end resistance. r w is one of the wiper resistance s contributed by the on resistance of an internal switch. the ad5290 wiper s witch is designed with the transmission gate cmos topology and with the gate vol tage derived from v dd . the wiper resistance, rw, is a function of v dd and temperature. contrary to the temperature coefficient of the r ab , which is only 35 ppm/c, the temperature coefficient of the wiper resistance is significantly higher because the wipe r resistance double s from 25 c to 125 c. as a result, the user must take into consideration the contribution of rw on the desirable resistance . on the other hand, t he wiper res istance is insensitive to the tap point potential . as a result, rw r emains relat ively flat at a given v dd and t emperature at various codes . assuming that an ideal 10 k? part is used, the wipers first connection starts at the b terminal for the programming code of 0 x00 where swb is closed. the minimum resistance between terminal w and terminal b is, therefore, generally 15 0 ?. the second connection is the first tap point, which corresponds to 189 ? ( r wb = 1/256 r ab + 3 r w = 39 ? + 15 0 ?) for code 0x01, and so on. each lsb data value increase moves the wiper up the resistor ladder unti l the last tap point is reached at 10, 11 0 ?. i n the zero - scale condition, a finite total wiper resistance of 15 0 ? is present. regardless of which setting the part is oper - ating in, care should be taken to limit the current between the a terminal to b term inal , w terminal to a terminal , and w terminal to b terminal , to the maximum dc current of 5 ma or pulse current of 20 ma. otherwise, degradation , or possible destruction of the internal switch contact , can occur. similar to the mechanical potentiometer, the resistance of the rdac between the w terminal and the a terminal also produces a digitally controlled complementary resistance, r wa . r wa starts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equat ion for this operation is w ab wa rr d dr + ? = 3 256 256 )( (2)
ad5290 data sheet rev. c | page 16 of 20 programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper to b and wiper to a proportional to the input voltage at a to b. u nlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. a v i w b v o 04716-013 figure 28 . potentiometer mode configuration if ignoring the effect of the wiper resistance for simplic ity, con - necting the a terminal to 30 v and the b terminal to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 1 lsb less than 30 v. each lsb of voltage is equal to the v oltage applied across terminal a and terminal b, div ided by the 256 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is b a w v d v d dv ? += 256 256 256 )( (3) operation of the digital p otentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors r wa and r wb and not the absolute values. therefore, th e temperature drift reduces to 5 ppm/c. 3- wire serial bus digi tal interface the ad5290 contains a 3 - wire digital interface ( cs , clk, and sdi). the 8 - bit serial word must be loaded msb first. the format of the word is shown in table 4 . the positive edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic fami - lies work well. when cs is low, the clock loads data into the serial register on each positive clock edge. the data setup and data hold times in the specifications section determine the valid timing requirements. the ad5290 uses an 8- bit serial input data register word that is transferred to the internal rdac register when the cs line returns to logic high. extra msb bits are ignored. daisy chain operatio n sdo shifts ou t the sdi content in the previous frame; thus it can be used for daisy - chain ing multiple devices. the sdo pin contains an open drain n - ch mosfet and requires a pull - up resistor if the sdo function is used. users need to tie the sdo pin of one package to th e sdi pin of the next package. users may need to increase the clock period because the pull - up resistor and the capacitive loading at the sdo to sdi interface can induce time delay to the subsequent devices. for example, in figu re 29 , if two ad5290s are daisy - chained, a total of 16 bits of data are required for each operation. the first set of eight bits goes to u2, and the second set of eight bits goes to u1. the cs should be kept low until all 16 bits are clocked into their respective serial registers. the cs is then pulled high to complete the operation. ad5290 u1 sdo sdi clk cs ad5290 u2 sdo sdi clk cs c +5v r pu 2.2k? mosi ss sclk 04716-014 figure 29 . daisy chain configuration
data sheet ad5290 rev. c | page 17 of 20 esd protection all digital inputs are protected with a series input resistor and a zener esd structure, as shown in figure 30 . these structures apply to digital input pins , pin cs , pin clk, pin sdi, and pin sdo. logic 340? gnd 04716-015 figure 30 . equivalent esd protection circuit all analog terminals are also protected by zener esd protection diodes, as shown in figure 31 . v ss v dd a w b 04716-016 figure 31 . equivalent esd protection analog pins terminal voltage operating range the ad5290 v dd and v ss power supplies define the boundary conditions for proper 3 - terminal digital potentiometer opera - tion. the ad529 0 can operate in single supply from +4.5 v to +33 v or dual supply from 4.5 v to 16.5 v. t h e ad5290 is functional at low supply voltage s such as 4.5 v, but the performance parameters are not guaranteed. the voltage s present on terminal a, terminal b, and terminal w that are more positive than v dd or more negative than v ss are clamped by the internal forward - biased diodes ( figure 31 ). power - up and power - down sequences because of the esd protection diodes that limit the voltage compliance at terminal a, terminal b, and terminal w ( figure 31 ), it is important to power v dd /v ss before applying any voltage to t erminal a, terminal b, and terminal w. otherwi se, the diodes are forward - biased such that v dd /v ss are powered unintentionally and affect the system. similarly, v dd /v ss should be powered down last. the ideal power - up sequence is as follows: gnd, v dd , v ss , digital inputs, and v a /v b /v w . the order of powe ring v a , v b , v w , and the digital inputs is not important, as long as they are powered after v dd /v ss . layout and power sup ply biasing it is good practice to use a compact, minimum lead -length layout design. the leads to the input should be as direct as poss ible, with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors. low equivalent series resistance (esr), 1 f to 10 f tantalum or e lectrolytic capacitors , should be applied at the supplies to minimize any transient disturbance and to filter low frequency ripple. figure 32 illustrates the basic supply - bypassing configuration for the ad5290 . the ground pin of the ad5290 is a digital ground reference. to minimize the digital ground bounce, the ad5290 digit al ground terminal should be joined remotely to the analog ground ( figure 32 ). v dd v dd v ss v ss gnd c3 ad5290 c4 c1 + + c2 10f 10f 0.1f 0.1f 04716-017 figure 32 . power supply bypassing
ad5290 data sheet rev. c | page 18 of 20 applications high voltage dac ad5290 can be configured as a high voltage dac, with out- put voltage as high as 30 v. the circuit is shown in figure 33. the output is )]1(v2.1[ 256 )( 1 2 r r d dv o ???? (4) where d is the decimal code from 0 to 255. ad5290 u2 op284 v+ v? op284 v out v dd u1b v dd r bias adr512 d1 r2 r1 b 100k ? 0 4716-018 u1a figure 33. high voltage dac programmable power supply with a boost regulator, such as adp1611 , ad5290 can be used as the variable resistor at the regulators fb pin to provide the programmable power supply (figure 34). the output is ] )( 1[v23.1 2 256 r r v ab d o ? ??? (5) ad5290 s v dd is derived from the output. initially, l1 acts as a short, and v dd is one diode voltage drop below +5 v. the output slowly establishes the final value. ad5290 adp1611 1.23v c c 150pf r c 220k ? c out 10 ? f v out d1 l1 4.7 ? h in gnd ss fb rt sw comp u2 c1 0.1 ? f v dd r1 100k ? a w b c in 10 ? f 5v r2 8.5k ? c ss 22nf 04716-019 u1 figure 34. programmable power supply audio volume control because of its good thd performance and high voltage capability, ad5290 can be used as a digital volume control. if ad5290 is used directly as an audio attenuator or gain amplifier, a large step change in the volume level at any arbi- trary time can lead to an abrupt discontinuity of the audio signal causing an audible zipper noise. to prevent this, a zero- crossing window detector can be inserted to the cs line to delay the device update until the audio signal crosses the window. since the input signal can operate on top of any dc level rather than absolute zero volt level, zero-crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. the configuration to reduce zipper noise (figure 35) and the results of using this configuration are shown in figure 36. the input is ac-coupled by c1 and attenuated down before feeding into the window comparator formed by u2, u3, and u4b (figure 35). u 6 is used to establish the signal zero reference. the upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 v and 2.497 v (or 0.005 v window) in this example. this output is anded with the chip select signal such that the ad5290 updates whenever the signal crosses the window. to avoid a constant update of the device, the chip select signal should be programmed as two pulses, rather than as one shown in figure 36. in figure 35, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window.
data sheet ad5290 rev. c | page 19 of 20 r1 100k ? r2 200? 5v v in v+ v? ad8541 5v u6 r3 100k ? r4 90k? r5 10k? c1 1f v dd v ss cs clk sdi v+ v? ad5290 100k ? +15v ?15v c3 0.1f c2 0.1f a b w gnd sdi clk cs u1 v+ v+ v? v? adcm371 adcm371 +15v ?15v +5v +5v u3 u2 v out u5 u4a u4b 16 2 4 5 04716-028 7408 7408 figure 35 . audio volume control with zipper noise reduction 04716-021 channel 1 freq = 20.25khz 1.03v p-p 1 2 figure 36 . input (trace 1) and output (trace 2) of the circuit in figure 35 ( the command of volume c hange may occur at any time , but the level chan ge occur s only near the zero - crossing window )
ad5290 data sheet rev. c | page 20 of 20 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 37 . 10- lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model 1 r ab (k? ) temperature range package description package option branding ad5290yrmz10 10 C 40c to +125c 10- lead msop rm -10 d4u ad5290yrmz10- r7 10 C 40c to +125c 10- lead msop rm -10 d4u ad5290yrmz50 50 C 40c to +125c 10- lead msop rm -10 d4t ad5290yrmz50 - r7 50 C 40c to +125c 10 - lead msop rm - 10 d4t ad5290yrmz100 100 C 40c to +125c 10- lead msop rm -10 d4v ad5290yrmz100- r7 100 C 40c to +125c 10- lead msop rm -10 d4v eval -ad5290 ebz 10 evaluation board 1 z = rohs compliant part. ? 2005 - 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04716 -0- 11/11(c)

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